The present invention relates in general to integrated circuitry, and in particular to methods and circuits for implementing a high frequency loss of signal detector.
In many telecommunication applications the receiver is required to distinguish between bad or corrupted data and valid data. Common causes of bad data include disconnects in the transmission line (e.g., a cut fiber optic cable in an optical network), excessive attenuation of the signal relative to noise or DC offset in the signal path, clock feed-through, or equipment fault. Bit error rate (BER) which is a direct indication of the number of errors in received data during a given time period is commonly used in the industry as a measure of the quality of the received signal. In some applications BER is measured by sending and receiving a known pattern, while other applications measure BER by a line loop-back test method. In order to continuously monitor BER of a received signal, receivers use a statistical loss of signal (SLOS) detector. The SLOS detector measures BER relative to a threshold and indicates a loss-of-signal condition when BER exceeds the threshold.
In a typical receiver, clock is extracted from the incoming data and is used to retime the incoming signal before further processing the data. BER increases when the timing relationship between the extracted clock and the incoming data falls outside the allowed range. For example, the retiming circuitry may require one edge, e.g., the falling edge, of the clock to occur in the middle of the data eye. If the clock falling edge gets too close to the data transition, an error may occur. Jitter and static phase offset are the two main contributors to disturbing the required phase relationship and therefore the increase in BER. Incoming data jitter as well as extracted clock jitter both add to the total jitter, and clock duty cycle distortion as well as clock and data recovery (CDR) and retimer phase offset all add to total static phase offset. The functionality of the SLOS detector can therefore be based on monitoring the phase of the data signal relative to that of the recovered clock signal. A 2.488 Gb/s fiber optic receiver that includes a loss-of-signal detector designed based on this concept is described in “A 2.448 Gb/s Si-bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection,” HP Design Conference, Tokyo, 1997,by Walker et al. That implementation, however, relies on a Si-Bipolar process to achieve the required speed of operation for 2.448 Gb/s receiver. The faster Si-Bipolar process and the relatively lower speed of operation relax some of the circuit design constraints. For example, for higher bit rates (e.g., 10 Gb/s or higher) the capacitive loading on the internal data and clock lines becomes far more critical. Because the SLOS circuitry often directly connects to the data input line and the recovered clock line, at higher data rates special care must be taken to minimize the capacitive loading on these lines. It is also desirable to implement the circuit in standard CMOS (complementary metal-oxide-semiconductor) transistor technology which is more cost-effective and has the added advantage of lower power consumption. The CMOS process, however, is a slower process compared to Si-Bipolar or other more complex processes such as SiGe or GaAs. Furthermore, the SLOS signal is often used to immediately initiate remedial action such as rerouting of signal traffic to a redundant cable, or adjusting the phase or threshold levels in certain internal circuitry, and the like. Such remedial actions are often disruptive and have undesirable side-effects. For overall system reliability, therefore, it is desirable that the SLOS detector operate reliably.
There is therefore a need for a loss-of-signal detector that can operate reliably at ultra-high data rates and can be implemented without requiring special processing technologies.